With the advent of polycrystalline silicon technology, the MOS transistor comprised of a layer of polysilicon disposed over a channel region and separated therefrom by a gate oxide has been a mainstay for the fabrication process of MOS transistors. In the early days of this technology, a conformal layer of polysilicon was first disposed over the substrate and then patterned to form the gate electrodes of the MOS transistors within the various active regions. Thereafter, this gate electrode was utilized as the mask to define the channel regions, wherein an implant step was operable to form source/drain regions on either side of the channel. This was acceptable for early integrated circuits, as the size of the transistors was quite large. However, as device sizes have been scaled down with the advent of new technology, the gate electrodes have become much narrower and thinner, this in and of itself presenting some difficulties and challenges to the designer.
The quality of a transistor is affected by the doping level in the polysilicon. Typically, the conductivity of the polysilicon is increased as much as possible and, therefore, it is heavily doped. In early CMOS devices, the polysilicon that was utilized to form the gate electrode was typically subjected- to a uniform doping of one impurity type, such as N-type impurities. For N-channel transistors, this resulted in the formation of an acceptable transistor. This was due to the fact that the majority carrier in the gate was opposite to the majority carrier in the channel region. In the P-channel device, the opposite condition was present. Typically, a threshold adjust implant was required in the P-channel transistor. As transistor technology advanced, the gate electrodes for P-channel transistors were doped separately from those for N-channel transistors, such that P-type impurities were introduced into the gate electrodes associated with P-channel transistors.
Typically, the doping level in the gate electrode is relatively high. This is for the purpose of minimizing the voltage dependency of the gate oxide thickness. For low doping levels in the gate electrode, a high voltage associated with a transistor that is turned on will result in a depletion region forming in the gate electrode adjacent to the gate oxide boundary. This will increase the effective gate oxide thickness. This can be detrimental to frequency response and other parameters of the transistor. By increasing the doping level, this depletion region is minimized, as majority carriers adjacent to the gate/oxide boundary are depleted. Of course, in some situations, such as that for high voltage transistors, it is desirable to have the gate oxide thickness increase with voltage. This, of course, is not true for small signal transistors.